1. Field of the Invention
The present invention relates in general to the field of data transfer on a parallel bus, and more particularly, to a mechanism for pre-driving during a master changeover on a parallel bus.
2. Description of Related Art
A multiprocessor system increases system performance because multiple processors operate in parallel. A typical multiprocessor system has a number of processors attached to a common host bus. Although each processor can only use the host bus one at a time, efficient bus protocol has been developed to optimize the host bus utilization.
In such a multiprocessor system, the data bus is the most critical resource because all information and data exchanges take place on the data bus. It is therefore important that the data bus is efficiently utilized. One way to maintain efficient bus utilization is to provide multiple data transfer rates, e.g., a normal transfer rate and a fast transfer rate. The normal transfer rate is typically the rate that is determined by the bus clock. The fast transfer rate, e.g. 2x, is typically a multiple of the normal transfer rate. To accommodate the fast transfer rate, the data transfer is typically clocked by two strobe signals which are phase shifted such that the active edges as provided by both strobes correspond to the fast transfer clock. The problem with this differential approach is that when there is a change in the bus ownership, i.e., when another master takes over the bus, there is a delay of at least two clocks. This two delay clocks, commonly referred to as "dead clocks", reduce the efficiency of the data transfer.
Accordingly, there is a need in the technology to have a mechanism to improve the dead time during master changeover on a parallel bus.